Marvell Technology

Since 2022, the Technical Leadership Mentoring Program has reached 63 senior technical leaders at Marvell across four cohorts, supported by more than 30 executive mentors. The 12-month program, sponsored by Corporate Chief Technology Officer Noam Mizrahi, combines immersive workshops, a leadership 360 assessment and 1:1 mentoring with executives. Participants learn to shape strategy, lead cross-functional work and influence teams they don’t manage. Distinguished Engineer Dan Scofield says the program changed how he thinks about his role, “not just as a technical resource, but as a connector and enabler for others.” Learn how the program develops technical leaders: mrvl.co/4eYin4I

Ara T can cut optical module power consumption by more than 35%. It’s part of the Marvell 1.6T optical DSP platform portfolio, which just earned a 2026 LEAP (Leadership in Engineering Achievement) Award from @DesignWorld in the connectivity category. The portfolio includes Ara T, the first 8x200G transmit-retimed optics DSP; Ara X, the first 1.6T DSP with advanced link reliability; Petra, the first 3nm 8x100G to 4x200G gearbox; and Aquila M, the first O-band-optimized coherent-lite DSP with integrated MACsec. Read more about the award-winning portfolio: mrvl.co/4ekLX4c

Are you looking for your next engineering role? Marvell is attending the Society of Women Engineers WE26 conference. Engineers from Women@Marvell will join our recruiters at the career fair to meet candidates for internships and full-time roles. Visit booth 3037 to meet the team. Learn more about careers at Marvell: mrvl.co/48z843m #WE26

AI clusters run at just 40-50% GPU utilization today. The bottleneck has moved from compute to memory to connectivity. In a new video, Rajagopal Krishnaswamy, AVP of Product Marketing for Cloud Switch at Marvell, shows a live Teralynx T100 running traffic at full wire speed. The T100 is the industry’s first monolithic 102.4 terabit per second Ethernet switch built on 3nm. Its programmable pipeline, adaptive routing and congestion signaling keep traffic moving so GPUs keep working. It’s also open and standards-based, so existing tools and operations carry over. Learn more about the performance, connectivity and programmability of Teralynx T100 Ethernet switches: mrvl.co/4koQoyy

As AI infrastructure scales and optical connectivity moves closer to compute, deeper integration of semiconductor and optical technologies is becoming essential to delivering the bandwidth, performance and power efficiency customers need. Marvell Chairman and CEO Matt Murphy and @Lumentum President and CEO Michael Hurlston joined CNBC's @SquawkStreet to discuss how the combination of the companies will create the category leader in AI connectivity. Watch the interview: mrvl.co/4jUwfAs Important information and disclosures: mrvl.co/3WJphEB

Today, Marvell announced an agreement to combine with @Lumentum, bringing together two of the fastest-growing enablers of AI to create a category leader in AI connectivity. As AI infrastructure scales and optical connectivity moves closer to compute, customers need increasingly integrated solutions that deliver greater bandwidth, performance and power efficiency. By combining Marvell's leadership in high-performance connectivity and semiconductor technologies with Lumentum's expertise in photonics, advanced lasers and specialized manufacturing, we expect to enable deeper co-design and innovation across the connectivity stack. Read the press release: mrvl.co/4sBzizH Important information and disclosures: mrvl.co/3WJphEB

Accelerator compute has roughly tripled every two years, while bandwidth between accelerators has grown only about 1.4x. That gap leaves expensive GPUs idle, waiting on data. Cornell’s Rachee Singh shared those figures at MemNetAI, the first workshop on Memory-Semantic Networking for AI-Scale Systems. Marvell launched it at ACM SIGCOMM 2026 with researchers from IIT Hyderabad and IIIT Delhi to explore a central question: once memory crosses a switched fabric, is it still memory or has it become a network? Read the recap of the talks on CXL, optical interconnect and the blurring line between memory and the network: mrvl.co/4kroCBv

Scale across is driving bandwidth growth of 10x to 20x between data centers. Is that still data center interconnect? Russ Esmacher, Senior Vice President and General Manager of Data Center Interconnect at Marvell, explains how connecting AI cluster to AI cluster differs from classical interconnect. The workloads are synchronized and latency sensitive, and the technology must deliver high performance in a pluggable package. See the conversation with @TheSixFiveMedia here: mrvl.co/4sp1bLf

Marvell experts are taking the stage at WISH Conference 2026, the flagship event from the @GlobalSemi Women’s Leadership Initiative. Approximately 1,000 technology leaders, entrepreneurs and STEM students will gather at the Santa Clara Convention Center to celebrate women’s achievements in technology, build networks and advance gender parity across the industry. Marvell engineers will lead a breakout session, join a main stage panel and present two posters on advanced packaging and optical modules. See the full lineup and learn more on our website: mrvl.co/4BtnbZw

AI infrastructure product cycles used to run 3 to 5 years. Now they run 12 to 18 months. Xi Wang, Senior Vice President and General Manager of the Connectivity Group at Marvell, describes how hyperscaler demand is changing. Requirements are more diverse, cycles are shorter and volumes can run 10 to 100 times higher than the previous generation. That’s why the company designs for high volume manufacturing from day one. View the full interview with @TheSixFiveMedia: mrvl.co/4sp1bLf

The copper wall has moved closer to the silicon. What does that mean for optics? As AI systems connect more accelerators, copper can’t keep up with the bandwidth needed inside the tray. Sandeep Bharathi, President of the Data Center Group at Marvell, explains why optics now reaches deeper into the rack and how the company’s silicon photonics portfolio and modulation schemes address the shift. Copper still has a role. Optics is where the bandwidth is heading. Watch the full conversation with @TheSixFiveMedia: mrvl.co/4sp1bLf

Marvell Fellow and Technical Vice President Jeanne Trinko Mechler will deliver a keynote at WINTECHCON 2026, the 7th IEEE International Women in Technology Conference. Her session, “AI and Machine Learning in Semiconductor Design and Manufacturing,” will explore how AI is transforming semiconductor design and accelerating innovation across the industry. With experience spanning more than 60 chip designs and a career at the forefront of AI silicon, chiplet technologies, and next-generation design methodologies, Jeanne brings a perspective that is both technically deep and broadly influential. Learn more: mrvl.co/4BtYbRW

Patrizia Mastromatteo spent years as a layout engineer, left Marvell after several years to explore other opportunities, and eventually came back. Her perspective on what changed, and what didn’t, is worth reading. As a Senior Staff Engineer in Pavia, Italy, Patrizia draws an unexpected parallel between her two passions: layout engineering and pastry arts. Both demand precision and process. Both also require imagination. In her words, once you find a methodology that works, your instinct is to repeat it, which is exactly what brought her back to Marvell. Her story also touches on teaching in the University of Pavia’s “From Micro to Macro” program, helping a new generation of engineers learn a profession she has spent more than 20 years perfecting. Read the full story here: mrvl.co/4jZwMAU

Agentic AI transforms inference from a compute problem into a distributed, memory-intensive systems challenge. KV cache state must be placed at the right performance tier with predictable latency and bandwidth, and no single technology solves that alone. At the AI Networking Summit 2026, Marvell Director of Solutions Architecture Ashwin Gopalan will present a systems architecture that addresses this challenge end to end, spanning on-package HBM, host-attached memory, a shared CXL-based KV cache tier, and durable storage, unified by a Teralynx Ethernet fabric delivering the high-throughput east-west connectivity required for agent coordination, cache movement, and multi-rack inference. Attendees will leave with a practical framework for designing AI infrastructure as an integrated compute, network, and memory system. Learn more: mrvl.co/4B5rlqf

Compute came first. Then memory. Now the real bottleneck is connectivity. In this clip from a recent @theCUBE conversation, Marvell Executive Vice President and General Manager of Custom Cloud Solutions Will Chu explains why connectivity has become the defining constraint in AI infrastructure, and why Marvell’s connectivity-first strategy, built on more than 20 years of investment, puts the company at the center of what comes next. Watch the full interview: mrvl.co/4s5SC86