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Joined January 2024
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Nvidia and the World Without Jensen Is NVIDIA Over? Export Controls, RASA, Open Source Implications, Supply Chain Implications, Affair, US Still Dependent On China newsletter.semianalysis.com/…
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BREAKING NEWS🚨: GB300 NVL72 can reach 1725 tok/s/user on DeepSeek v4.1 Flash using TP24 with TileRT MegaKernels, 2x faster than general-purpose engines for decode! More to come from the TileRT folks with multi-concurrency on GB300 NVL72. If you see what TileRT on GB300 NVL72 can do, imagine what TileRT on Rubin NVL72, MI455X UALoE72, or TPUv7 could do!! Great work by the TileRT maintainers, and thank you to Ian Buck for providing GB300 NVL72 access to this amazing TileRT project!
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BREAKING NEWS: Less than 3 weeks since the MiniMax M3.1 Flash launch, NVIDIA and @Inferact have already submitted an initial vLLM Rubin NVL72 submission that is state-of-the-art and delivers 6.5x better perf per TCO than GB300 NVL72. Great to see that Rubin is already becoming more and more mature and integrated in partnership with @vllm_project! This Rubin submission uses the new locality-aware MoE feature in CUDA 13.4, which reduces latency and increases realized HBM bandwidth by ~1.2x.
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BREAKING: Nvidia employee who reportedly had an affair with Nvidia CEO Jensen Huang identified as VP of Healthcare Kimberly Powell
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Google has unveiled TPU 8i Max, aka Whalefish. One interesting detail is that the announcement confirms the 8i Max will have 384GB of HBM per chip, meaning it moves to 8-hi HBM compared to the 12-hi HBM used for the original TPU 8i, which we reported to Accelerator Model subscribers several months ago. This follows Nvidia's move to move to 8-hi HBM for next generation Rubin Ultra. Google is advertising much stronger inference performance TPU 8i Max as each package now has double the HBM bandwidth. Bandwidth is more important than capacity for inference performance as we explained recently in our 4-hi HBM article which you can read here: newsletter.semianalysis.com/…
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MOG ALERT🚨: NVIDIA, in partnership with @radixark, has just improved SGLang Rubin performance again by up to 10x in less than 5 days!!
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SpaceX is developing Kessel, a custom Vera Rubin NVL72 rack that replaces internal NVLink cable cartridges with a passive PCB midplane. It keeps Oberon’s 72 GPU packages, 18 compute trays and 9 switch trays, but rearranges them back-to-back around the board. Think mini Kyber, with a smaller scale-up domain and a design intended for both terrestrial and orbital deployment. The question is whether this smaller version can make the midplane practical. (1/4)🧵
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The manufacturing difference is substantial: Kessel specifies an 84-layer M10 midplane, versus 156 layers of M9 planned for the earlier Kyber design. Fewer layers give it a more feasible manufacturing path, although the design requires a higher-grade material. (2/4)
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We visited Galaxy, Envision's 800MW wind-powered datacenter campus in Ulanqab, Inner Mongolia. Its first 120MW phase went from bare land to delivery within a year. (1/6)🧵
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On power, Galaxy runs a 5MW pilot hall on solid-state transformers. They take 10kV AC from the grid and convert it to 800V DC that goes straight to the racks. In the US, this design is still on the roadmap. (2/6)
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Take a look 👀 sales@semianalysis.com | semianalysis.com/careers
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Fable 5.2 is very token inefficient for certain tasks due to its increased persistence and proclivity for spawning subagents. For example, on GDPx materials science tasks, Fable 5.2 costs 89% more than Astra and uses 4.3x more output tokens to achieve effectively the same score. The price difference vs Gemini 4 Carbon is even more startling at 7.5x. (1/3)🧵
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Similarly, Fable 5.2 uses 2.3x more output tokens than Opus 5.5 to achieve a marginally worse partial score on GDPx finance tasks. (2/3)
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🚨 HBM5 Doubles Bandwidth Without Adding a Single Pin 🚨 HBM5 keeps the same 2048 pins as HBM4E and runs each one nearly 2× faster. Samsung's Hot Chips 2026 presentation shows pin speed going from 14 Gbps on HBM4E to over 28 Gbps on HBM5. Faster pins are only half the story. To keep each pin fed, everything behind the pins doubles too: DRAM banks, TSVs, and an upgraded PHY on the base die. Here's how it works, explained as a grocery store 🛒 (1/6)🧵
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HBM4 already doubled the number of pins from 1024 to 2048. The GPU's shoreline has limited additional space, so HBM5 keeps the same number of pins and makes each one faster to improve bandwidth. (2/6)
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Fable 5.2 debuts at the top of the GDPx leaderboard scoring 16.4%. (1/7)🧵
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The gains are primarily concentrated in chip design and software engineering. Fable 5.2 beats Opus 5.5 by 10.8% and 15.5% respectively. (2/7)
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BREAKING NEWS🚨: Today, Google announces TPU 8tx for confidential inference and TPU 8i Max! This builds on the rapid progress they are making across the TPUv7 inference stack, much of which can, at a high level, be transferred to the TPUv8 series, including Muse Spark Open, @sgl_project and @radixark. TPUv7 MOGGING GB300 NVL72!
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The biggest risk to the US data center buildout is already in effect in one state. “The single biggest risk isn’t a single candidate, because in many cases both parties and candidates want developers to accept stricter terms.” “In the case of Texas, it’s a freeze that already exists. Texas stopped issuing TCEQ permits to data center projects at the end of September, on top of an ERCOT interconnection audit that started in August.” “Texas alone is close to 30% of US additions in 2028. So a few months of lost time in that one state, that one market, could move the national number.”
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CXMT is talking up its 4F² DRAM roadmap again. At its October 30 earnings briefing, the company mentioned its first 4F² DDR5 RDIMMs are targeted for sampling by year-end. (1/6)🧵
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As we discussed in our October 16 note, the economics depend on the actual dimensions and manufacturing process behind the 4F² label. (2/6)
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ALERT🚨🚨: AMD MI355 is 1.42x FASTER THAN GB300 NVL72. THIS IS ACHIEVED USING THE TILERT SOFTWARE, WHICH GETS 1330 p90 tok/s/user on long context workloads! Thanks to AMD leadership for providing an MI350 cluster to TileRT maintainers, enabling them to achieve this great result!
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We Visited China’s Stargate in Inner Mongolia A wind-powered 800MW campus, 120MW built within a year, a 5MW SST-native 800V DC pilot and a cooling design without central chillers newsletter.semianalysis.com/…
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After DeepSeek V4.1 Flash, Xiaomi MiMo is moving to a causal encoder-decoder for its next-gen models. HySparse2: prompts run through only 25 of 49 layers. Decoder KV is projected from encoder states. At 1M context vs MiMo-V2: 5x less prefill compute, 4.5x smaller KV cache.
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We think tighter GPU financing is more likely to support rents than create a compute glut, because it slows new deployments while demand remains tight. (1/3)🧵
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Of the ~50 GW of datacenter capacity due online in 2027, we estimate at most 2–3 GW is at risk. Meanwhile, one-year H100 contract prices are up ~21% since March 2026, with customers committing to pay those rates for a full year. This is the key metric that reflects the longer-term customer commitments that underpin GPU rental economics. (2/3)
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Brand new ultra low CTE glass cloth - Vlex, it is an ultra-low thermal expansion glass cloth being developed by Nittobo for the next generation of larger semiconductor package substrates. As substrates grow, controlling dimensional changes during heating and cooling becomes increasingly important. Vlex is designed to help manufacturers manage that challenge by lowering the coefficient of thermal expansion, or CTE, of the glass reinforcement used in copper-clad laminates. (1/2)🧵
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Vlex glass has a CTE of 2.0 parts per million per degree Celsius between 50°C and 200°C. That is lower than its T glass at 2.8, NE glass at 3.3, and conventional E glass at 5.6. Vlex has a tensile modulus of 71 GPa, placing it above NE glass but below the stiffer T glass. At 10 GHz, its dielectric constant is 4.7 and its dissipation factor is 0.0043. These figures suggest a material aimed at balancing dimensional stability, mechanical properties, and electrical performance. (2/2)
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